1. Field of the Invention
The invention relates to multilayer or Three Dimensional Integrated Circuit (3D IC) devices, structures, and fabrication methods.
2. Discussion of Background Art
Performance enhancements and cost reductions in generations of electronic device technology has generally been achieved by reducing the size of the device, resulting in an enhancement in device speed and a reduction in the area of the device, and hence, its cost. This is generally referred to as ‘device scaling’. The dominant electronic device technology in use today is the Metal-Oxide-Semiconductor field effect transistor (MOSFET) technology.
Performance and cost are driven by transistor scaling and the interconnection, or wiring, between those transistors. As the dimensions of the device elements have approached the nanometer scale, the interconnection wiring now dominates the performance, power, and density of integrated circuit devices as described in J. A. Davis, et. al., Proc. IEEE, vol 89, no. 3, pp. 305-324, March 2001 (Davis).
Davis further teaches that three dimensional integrated circuits (3D ICs), i.e. electronic chips in which active layers of transistors are stacked one above the other, separated by insulating oxides and connected to each other by metal interconnect wires, may be the best way to continue Moore's Law, especially as device scaling slows, stops, or becomes too costly to continue. 3D integration would provide shorter interconnect wiring and hence improved performance, lower power consumption, and higher density devices.
One approach to a practical implementation of a 3D IC independently processes two fully interconnected integrated circuits complete with transistors and wiring, thins one of the wafers, bonds the two wafers together, and then makes electrical connections between the bonded wafers with Thru Silicon Vias (TSV) that are fabricated prior to or after the bonding. This approach is less than satisfactory as the density of TSVs is limited, because they require large landing pads for the TSVs to overcome the poor wafer to wafer alignment and to allow for the large (one to ten micron) diameter of the TSVs due to the thickness of the wafers bonded together. Additionally, handling and processing thinned silicon wafers is very difficult and prone to yield loss. Current prototypes of this approach only obtain TSV densities of 10,000 s per chip, in comparison to the millions of interconnections currently obtainable within a single chip.
By utilizing Silicon On Insulator (SOI) wafers and glass handle wafers, A. W. Topol, et. al., in the IEDM Tech Digest, p 363-5 (2005), describe attaining TSVs of tenths of microns. The TSV density is still limited due to misalignment issues resulting from pre-forming the random circuitry on both wafers prior to wafer bonding. In addition, SOI wafers are more costly than bulk silicon wafers.
Another approach is to monolithically build transistors on top of a wafer of interconnected transistors. The utility of this approach is limited by the requirement to maintain the reliability of the high performance lower layer interconnect metallization, such as, for example, aluminum and copper, and hence limits the allowable temperature exposure to below approximately 400° C. Some of the processing steps to create useful transistor elements require temperatures above 700° C., such as activating semiconductor doping or crystallization of a previously deposited amorphous material such as silicon to create a poly-crystalline silicon (polysilicon or poly) layer. It is very difficult to achieve high performance transistors with only low temperature processing and without mono-crystalline silicon channels. However, this approach may be useful to construct memory devices where the transistor performance is not critical.
Bakir and Meindl in the textbook “Integrated Interconnect Technologies for 3D Nanosystems”, Artech House, 2009, show a 3D stacked Dynamic Random Access Memory (DRAM) where the silicon for the stacked transistors is produced using selective epitaxy technology or laser recrystallization. This concept is unsatisfactory as the silicon processed in this manner has a higher defect density when compared to single crystal silicon and hence suffers in performance, stability, and control. It also requires higher temperatures than the underlying metallization could be exposed to without reliability concerns.
Sang-Yun Lee in U.S. Pat. No. 7,052,941 discloses methods to construct vertical transistors by preprocessing a single crystal silicon wafer with doping layers activated at high temperature, layer transferring the wafer to another wafer with preprocessed circuitry and metallization, and then forming vertical transistors from those doping layers with low temperature processing, such as etching silicon. This is less than satisfactory as the semiconductor devices in the market today utilize horizontal or horizontally oriented transistors and it would be very difficult to convince the industry to move away from the horizontal. Additionally, the transistor performance is less than satisfactory due to large parasitic capacitances and resistances in the vertical structures, and the lack of self-alignment of the transistor gate.
A key technology for 3D IC construction is layer transfer, whereby a thin layer of a silicon wafer, called the donor wafer, is transferred to another wafer, called the acceptor wafer, or target wafer. As described by L. DiCioccio, et. al., at ICICDT 2010 pg 110, the transfer of a thin (tens of microns to tens of nanometers) layer of mono-crystalline silicon at low temperatures (below approximately 400° C.) may be performed with low temperature direct oxide-oxide bonding, wafer thinning, and surface conditioning. This process is called “Smart Stacking” by Soitec (Crolles, France). In addition, the “SmartCut” process is a well understood technology used for fabrication of SOI wafers. The “SmartCut” process employs a hydrogen implant to enable cleaving of the donor wafer after the layer transfer. These processes with some variations and under different names are also commercially available from SiGen (Silicon Genesis Corporation, San Jose, Calif.). A room temperature wafer bonding process utilizing ion-beam preparation of the wafer surfaces in a vacuum has been recently demonstrated by Mitsubishi Heavy Industries Ltd., Tokyo, Japan. This process allows room temperature layer transfer.